Impinj

Multi-Node FPGA System for Wireless Protocol Development

This student team will work to create a system to manage real-time communication with a population of FPGA's emulating Impinj RAIN RFID Tags. This system should be able to send sequences of valid and invalid commands to the tag emulators and simulate real-world RF conditions by programming varied RF attenuation among the FPGA tag emulators. Upon completion, this project will aid Impinj in pre-silicon testing of RFID tag functionality and performance in many-tag systems. This would improve on current pre-silicon tag testing which focuses on RTL and post-layout simulation of single tag designs, and it would provide a method to gather new, scenario-dependent performance metrics. Students will be provided working FPGA RFID tag emulators and access to a Linux host and software suite that can send and receive communications with a single tag emulator. Using the example one-tag system, students will be tasked with designing a host system (wireless or wired) that can send and receive sequences of communications to and from a population of "many" tag emulators. The system should be able to program varying attenuation to different tag emulators in the system to emulate variations in RF signal strength in real tag populations. The system will be tested using RAIN Gen2 RFID protocol algorithms, but knowledge of the protocol is not necessary because algorithms will be provided. Once the students have created the system described, students can tackle reach goals by testing a variety of situations and gathering exciting new performance metrics about RFID tags in real-world scenarios. The minimum expectation for this project is that students will deliver a system that can communicate and control, either wired or wirelessly, at least 5 FPGA tag emulators and create different RF conditions on each emulator. Additionally, the system created should automate deployment of different tag architectures across tag emulator population. Desired outcomes could include creating a system that could communicate with as many as 25 FPGA tag emulators or collect and control internal logic states and memory from the FPGAs and leverage the data to evaluate performance of provided algorithms.