Micron

Systematic Variation of Transistor Characteristics From High Volume Wafer Fabrication

In this project, students will leverage their engineering and data science skill sets to tackle a real world manufacturing data set. The initial stage of the project will focus on data engineering, analysis, and method building. Upon assessment of data correlations, students will narrow scope and dig deeper into a portion of semiconductor fabrication process to identify root cause. DRAM CMOS and/or interconnect devices exhibit systematic variation in threshold voltage resulting from the hundreds of process steps use to fabricate them. We suspect that some process variation [tool-to-tool, wafer-to-wafer] is directly correlated. Identify the process steps, whose variability have the greatest influence on wafer level parametrics (Vt, Resistance, Capacitance, etc). Under this problem statement, students will identify influential process steps and attempt to build a physical root cause assessment. Additional data or process details may be provided on a need base as the project proceeds. Through this project students will have the opportunity to utilize their engineering and data science training on a real world problem set and network, with the intent of exploring careers in the growing area of domestic semiconductor manufacturing and R&D.